Logic Gate

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logic_gate

Element-wise boolean logic: AND, OR, NOT, NAND, NOR, XOR, XNOR

Signature

Inputs

aSignalrequired
bSignal

Outputs

resultSignal

Parameters

Key	Type	Default	Notes
`gate`	enum	and	one of: and, or, xor, nand, nor, xnor, not
`threshold`	float	0.5

Description

Logic Gate applies a Boolean gate element-wise to one or two signals: and, or, xor, nand, nor, xnor, or the unary not. Each input sample is first thresholded to a Boolean by comparing it against threshold (default $0.5$ ): a sample is logic-high when its value is $\geq$ the threshold, otherwise logic-low. The selected gate is then evaluated per element and the result port emits $1.0$ for true and $0.0$ for false, with the same length as a.

Input b is optional. When b is absent it is treated as logical false everywhere, so or/xor reduce to a pass-through of a's thresholded state and and/nor behave accordingly. The unary not ignores b entirely and inverts the thresholded state of a.

The node is stateless — output depends only on the current samples, with no memory or feedback. The output is a dimensionless Boolean level: physical units on the inputs are consumed by the thresholding step and are not propagated to result (compare the threshold against a bare number in the input's own scale). Because thresholding is a hard, non-differentiable decision, input uncertainty ( $σ$ ) does not flow through as a meaningful sigma on the ${0, 1}$ output and is dropped.

Mathematics

\tilde{a}_{i} = {10 a_{i} \geq θ a_{i} < θ, \tilde{b}_{i} = {10 b_{i} \geq θ otherwise

result_{i} = ⎩ ⎨ ⎧ \tilde{a}_{i} \land \tilde{b}_{i} \tilde{a}_{i} \lor \tilde{b}_{i} \tilde{a}_{i} \oplus \tilde{b}_{i} \neg (\tilde{a}_{i} \land \tilde{b}_{i}) \neg (\tilde{a}_{i} \lor \tilde{b}_{i}) \neg (\tilde{a}_{i} \oplus \tilde{b}_{i}) \neg \tilde{a}_{i} and or xor nand nor xnor not

Examples

Windowed alarm from two thresholds

Combine two comparator outputs (already $0/1$ ) with an and gate at threshold = 0.5 to raise result = 1.0 only where both conditions hold — e.g. temperature high and pressure high. With inputs at logic levels, the $0.5$ threshold cleanly separates the two states.

Analog-level XOR edge marker

Feed a raw analog ramp into a and a shifted copy into b with gate = xor, threshold = 2.5. Each channel is thresholded at $2.5$ , and result is $1.0$ only where exactly one channel crosses the level — marking the region between the two crossings.

a = [1, 2, 3, 4, 5],  b = [3, 3, 3, 3, 3],  threshold = 2.5
tilde_a = [0,0,1,1,1],  tilde_b = [1,1,1,1,1]
result  = [1,1,0,0,0]

Applications

Combinational control logic in simulation: gating actuator enables on multiple simultaneous sensor conditions.
Digital signal decoding and protocol analysis, e.g. XOR-based parity checks or Manchester edge detection on thresholded logic lines.
Fault and interlock logic in test benches, where `nand`/`nor` implement safety trip conditions from analog trip points.
Masking and event flagging in data pipelines: converting analog threshold crossings into Boolean masks that select or gate downstream samples.

Neat

Every gate is built from a single shared thresholding front-end, so a Boolean $0/1$ input and an analog input at the same threshold produce identical logic — the node needs no separate 'digital' mode.

With `b` disconnected, `xor` and `or` become identity-of-truth on `a` while `xnor` and `nand` become `not a`, giving you a unary inverter for free without switching to the `not` gate.

Known issues

Thresholding uses a $\geq$ comparison, so a sample sitting exactly on the threshold is classified as high; floating-point rounding of upstream computations can flip borderline samples between $0$ and $1$.

If `b` is shorter than `a`, gate evaluation follows `a`'s length; check that both inputs are aligned, since a mismatched or absent `b` silently contributes logical false rather than erroring.